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31. When both the input conditioning and main-gate flip-flop are logically true, the main gate opens for a period of time that is determined by the timer base divider.

32. The SR Flip-Flop is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates.

33. If the trapping mode flip-flop is set and the program includes any one of certain instructions, the instruction is not performed but the next instruction is taken from location N.

34. In this case, the position of the flip-flop in the chain determines its weight; i. e. , for a binary counter, the "power of two" it corresponds to.

35. Because of edge triggered flip-flop, a machine period is equal to a clock period, which improves the execution efficiency.

36. Then based on the characteristic of shift-register, we use the five-valued D flip-flop as the core component to design five-valued bidirectional shift-register.

37. We use a digital mixer realized with a D flip-flop flipped by a high potential to mix two independent clocks and sample the high frequency data input with the low frequency clock input.

38. SPICE simulation of the circuit indicates that body resistance has obvious influence on the speed of BC (body contact) D flip-flop circuit.

39. Especially, the clock-racing multi-threshold flip-flop can decreases the leakage power and the power dissipation of clock network.

40. Based on the basic circuit of maintaining block D flip-flop, the paper discusses how to solve this problem with JKflip-flop by adding another 3 logic gates in this paper.

41. Third, compare the lengths of two time signals through a D type flip-flop as a timing comparator. Finally, output approximated correspond digital value from temperature data through SAR.

42. In this thesis we build a model based on a D flip-flop chain and use a statistical method to evaluate the transmission quality of digital logic circuit affected by jitter and skew.

43. d flip-flop with the main design of the timing circuit.

44. Simulation results agree with the experiments. Finally, a frequency detection of a humidity sensor output with this D flip-flop differential frequency method is presented.

45. Three triggered ways of the flip-flop which are master-slave flip-flop, pulse flip-flop, edge-triggered flip-flop, is analyzed and compared in the paper.

46. Then based on the characteristic of reversible counter, four-valued D flip-flop was used as the core component to design four-valued synchronous reversible counter which has reset function.

47. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop.

48. Compared to high heels, they don't look remotely hazardous. But flip-flop wearers would do well to think twice before slipping on a pair.

49. This flip-flop has correct logic function as a dynamic D flip-flop, and has the distinct advantage of simple structure, small chip area, and simple two-phase clock.

50. D latch and D flip-flop circuits using floating-gate MOS are designed. In order to introduce the application of D flip-flop, we design the register and counter by D flip-flops.

51. But there a vast meadow of the, where the bad and the good flip-flop acrobatically.

52. To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation[http://sentencedict.com], this paper proposes the logic design of low power flip-flop based on double edge trigger.

53. The first kind of circuit is made up of flip-flop and gate circuit. The second is consisted of medium scale integration.

54. Through analyzing its work principle, we find the method to raise the speed: use a novel CMOS dynamic D flip-flop and an improved synchronous frequency divider.

55. The lack of support of the flip-flop also causes pain in the tendons on the inside of the foot and lower leg. It can also lead to shin splints.

56. The ECL OR-AND-gate can simplify a generalized ECL circuits structures, for example, an ECL double-edge-triggered D flip-flop.

57. Hex D flip-flop with common clock and reset. High-performance silicon-gate CMOS.

58. In this paper the relations of the various kinds of function of the flip-flop have been studied and a standardized method of functional transformation between flip-flops presented.

59. The term "consistency" describes the correct state of data resource stored in the system. VFP maintains the data consistency from data validity, flip-flop and quotation integration.

60. From function equations of different kinds of flip-flop integrated circuits, we discussed the methods of function change from final product JK of D flip-flop to other kind in use.