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1. Presents a circuit of FIFO involving single port SRAM.

2. The SRAM cell illustrated Kuhn's point as she showed the evolution from 90 - nm to 45 - nm design.

3. A 32KB Static Random Access Memory (SRAM), which is widely used at present in VLSI, is designed in this paper.

4. The access time of SRAM is 15 ns by optimizing the system.

5. In one embodiment, the semiconductor device includes a static random access memory (SRAM) cell having numerous NFETs (110) and PFETs (112).

6. It consists of a digital controller, SRAM for display data memory, a DC-DC voltage converter, reference current generators, a pre-charge voltage generator, 64 common drivers,[sentencedict .com] and 132 segment drivers.

7. As a class of most important cache for the embedded IP application, Static Random Access Memory (SRAM) has become one of the hottest research topics in the digital integrated circuits field.

8. SRAM FPGA system soft simulation designed to realize bitwise write bitwise Reading.

9. A practical design of a dual - port SRAM embedded in OLED display driver ICs was presented.

10. All byte wide memories have standard SRAM pinouts. they operate like SRAMs and provide nonvolatile storage with no requirement for battery backup.

11. In the design of SRAM memory array , we often meet with the problem about cross talk which is brought about by adjacent signal wire and node coupling.

12. I was pretty stoked when SRAM pr honch Michael Zellman called me up and actually offered to come to my house to install a complete group set on my bike. No lie!

13. It is commonly believed that SRAM belongs to the volatile semiconductor memory.

14. Decoder is one of the most important components in a memory unit, and its improvement can greatly diminish the access time of both register file and SRAM.

15. The optimization of cell static noise margin enhances the anti-jamming ability of SRAM.

16. But while promoted as universal memory density of MRAM doesn't approach that of DRAM or SRAM.

17. It has adopted a kind of frame store method that utilize SRAM chip to solve the collection of video signal.

18. The Phase I grant supported a six-month effort to develop a low-power 'green' battery with a 30-plus year shelf life that will power a SRAM (static random access memory) circuit for a computer device.

19. Sometimes, the contents of a ROM chip are copied to SRAM or DRAM to allow for shorter access times (as ROM may be slower).

20. Single event multiple upset ( SEMU ) experimental results of high - density static random access memory ( SRAM ) are presented.

21. Single event upset maps and cross-section curves obtained from numerial simulation show excellent agreement with broad beam cross section curves and micro-beam upset images for 2 kbit hardened SRAM.

22. DMA controller was used to transfer network data frame directly between the TRI and exterior SRAM without the interposition of embedded MCU. It can reduce the burden of MCU.

23. After analyzing the producing mechanism of leakage power for each sub-circuit in SRAM, A leakage power model for each sub-circuit was established to estimate the leakage power for full SRAM.

24. New design of programmable memory BIST for embedded dual ports SRAM is presented based on analyzing faults model.

25. We also apply this method in the floor plan of register file and SRAM layout, and gain a good result.

26. According to the requirement of the real-time anti-collision system the frame memory system uses two-steps of SRAM to achieve the parallel process between the data gathering and process.

27. As the cache memory of ULSI and CPU , SRAM occupies a significant the chip area.